Ineffective decoupling and grounding of high speed digital
logic systems is a major cause of radiated and conducted emissions, as
well as increased susceptibility to both internal and external noise sources.
Most designers still use the 40 year old technique of placing a 0.1 uF
capacitor next to an IC to provide decoupling without any analytic understanding,
or empirical verification, of the effectiveness of this approach.
This one-day seminar covers the mechanisms by which digital logic circuits generate noise, and the effectiveness and limitations of the various approaches to decoupling and grounding. Methods of overcoming these limitations by the use of multiple capacitors, ferrites, distributed capacitance, and isolated power planes are investigated. The interactions between ground plane, power plane, and the decoupling capacitance are discussed. The significance of ground voltage drop, and methods of minimizing it are also presented. Participants will gain a better understanding of the limitations of traditional decoupling methods and a knowledge of new technology and modern approaches to overcome these limitations.
Outline